Interface State Density Analysis for Novel Semiconductor Devices

Interface state density (Dit) analysis is a critical characterization technique for evaluating the quality of the semiconductor-dielectric interface in advanced devices such as SiC MOSFETs, GaN HEMTs, high-k CMOS gate stacks, and emerging 2D-material transistors. Accurate measurement of interface traps enables device engineers to optimize gate dielectric processes, recover channel mobility, suppress threshold voltage instability, and ensure long-term reliability. This article presents the technical principles, applicable samples, testing items, measurement methods, and typical applications of interface state density analysis for next-generation semiconductor devices.

Technical Overview

Interface states are electronic energy levels physically located at the boundary between a semiconductor and a gate dielectric. They originate from unsaturated dangling bonds, structural disorder, stoichiometric discontinuities, impurities, and interfacial chemical reactions such as carbon residue at the SiC/SiO2 interface or nitrogen-related defects in nitrided oxides. Because these states reside within the semiconductor bandgap, they act as carrier traps and generation-recombination centers, exchanging charge with the channel on time scales ranging from microseconds to hours.

Interface state density, typically denoted Dit and expressed in units of cm-2eV-1, quantifies the number of traps per unit area per unit energy within the bandgap. Its energy distribution is a direct figure of merit for the electrical quality of a gate stack. For mature Si/SiO2 interfaces, Dit can be reduced to the low 1010 cm-2eV-1 range, whereas wide-bandgap semiconductors such as 4H-SiC, GaN, Ga2O3, AlN, and diamond commonly exhibit Dit values of 1011 to 1013 cm-2eV-1, which severely degrades device performance.

Elevated interface state densities produce a range of well-documented device-level consequences, including:

• Threshold voltage shift and gate bias hysteresis caused by trapped charge
• Channel mobility degradation due to Coulomb scattering by occupied traps
• Deteriorated subthreshold swing and reduced on/off current ratio
• Increased 1/f noise and random telegraph noise in analog and RF circuits
• Accelerated bias temperature instability (BTI) and time-dependent dielectric breakdown (TDDB)
• Reduced photon detection efficiency and increased dark current in optoelectronic devices

Consequently, quantitative Dit analysis is an essential step in gate dielectric development, process integration, reliability qualification, and failure analysis for all novel device platforms. Measurements are performed in accredited third-party laboratories using internationally recognized methods aligned with JEDEC, SEMI, IEC, and ASTM practices.

Testing Samples

MOS and MIS Capacitor Structures

Metal-oxide-semiconductor (MOS) or metal-insulator-semiconductor (MIS) capacitors are the standard test vehicles for Dit extraction because they allow clean, unambiguous capacitance-voltage analysis. Samples may be fabricated on silicon, 4H-SiC, GaN, Ga2O3, GaAs, InGaAs, AlN, or diamond substrates with dielectrics such as SiO2, HfO2, Al2O3, ZrO2, Si3N4, or laminated stacks. A known gate area and a low-resistance ohmic back contact are required.

Transistor Test Structures

Actual MOSFETs, MISFETs, trench-gated power devices, and GaN MIS-HEMTs can be characterized directly using charge pumping, threshold hysteresis, and noise-based techniques. This allows Dit to be evaluated on fully processed devices rather than only on monitor capacitors.

Advanced and Emerging Device Platforms

• SiC planar and trench MOSFETs, including nitrided (NO/N2O annealed) gate oxides
• GaN and AlGaN/GaN MIS-HEMTs with in-situ or atomic layer deposited gate dielectrics
• High-k metal gate (HKMG) stacks for FinFET, gate-all-around, and nanosheet CMOS
• Two-dimensional material transistors, such as MoS2, WS2, and h-BN encapsulated channels
• Ferroelectric and charge-trap memory gate stacks (HfZrO, SONOS-type structures)
• Vertical Ga2O3 and diamond Schottky-barrier or MOS-based power devices

Samples may be submitted as full wafers (up to 200 mm or 300 mm), cleaved die, or packaged parts with accessible gate and body terminals. Minimum recommended MOS capacitor diameter is typically 100 µm to ensure adequate measurement capacitance.

Testing Items

The following electrical parameters related to interface and near-interface traps can be quantified:

• Energy-resolved interface state density distribution, Dit(E), across the semiconductor bandgap
• Integrated total interface trap density over a specified energy window
• Distinction between fast interface states and slow border/near-interface oxide traps
• Effective fixed oxide charge and its contribution to flatband voltage shift
• Gate bias hysteresis and threshold voltage instability under DC and pulsed stress
• Capture cross-section and emission time constants of interface traps
• Temperature dependence of trap activation and exchange dynamics
• Stretch-out and frequency dispersion characteristics of C-V curves
• 1/f noise power spectral density and its correlation with trap density

Testing Methods

High-Low Frequency C-V Method (Hi-Lo)

The most widely applied technique compares a quasi-static (low-frequency) C-V curve with a high-frequency (typically 100 kHz to 1 MHz) C-V curve. Interface traps respond at low frequency but not at high frequency, so the capacitance difference yields Dit via the standard hi-lo extraction formula. The method is robust and rapid, with a practical detection floor near 1010 to 1011 cm-2eV-1.

Conductance Method (G-omega)

Measuring the equivalent parallel conductance Gp as a function of frequency, bias, and temperature provides the highest accuracy for trap densities between approximately 1010 and 1012 cm-2eV-1. The loss peak of Gp/omega versus frequency also reveals trap time constants and capture cross-sections, and it accounts for the continuum of time constants produced by trap communication with the conducting channel.

Terman Method

The Terman method extracts Dit from the stretch-out of high-frequency C-V curves relative to an ideal theoretical curve. It is most suitable for lightly doped substrates and moderate Dit levels, and is often used as a cross-check against the hi-lo method.

Quasi-Static C-V and Berglund (C-psi-s) Method

The quasi-static technique measures the low-frequency capacitance using a slow voltage ramp or a step-response approach. Combining it with surface potential extraction enables direct determination of the interface state distribution without assuming a high-frequency reference.

Charge Pumping

For transistor structures, a periodic pulse applied to the gate while measuring the substrate or body current provides a very sensitive Dit measurement, reaching the 109 cm-2eV-1 range. Variable-frequency and variable-amplitude charge pumping further separate fast interface traps from slow border traps.

Deep Level Transient Spectroscopy (DLTS and CCDLTS)

Capacitance-mode and current-mode DLTS characterize deep traps by their thermal emission signatures, providing activation energies and apparent capture cross-sections. These methods are valuable for separating true interface states from bulk deep levels in epitaxial layers.

Slow Trap Pumping and Bias Temperature Stress

Particularly important for SiC MOSFETs, slow trap pumping quantifies near-interface oxide traps that respond on second-to-hour time scales. Combined with positive and negative bias temperature instability stress, it evaluates the trap generation expected under realistic operating conditions, consistent with JEDEC reliability guideline practices such as JEP180 for SiC power MOSFETs.

Low-Frequency Noise Spectroscopy

1/f noise measurements on transistors correlate the normalized noise amplitude with the density of traps located near the Fermi level, offering a non-destructive, die-level indicator of interface quality.

All measurements are performed using precision impedance analyzers, LCR meters, semiconductor parameter analyzers, and cryogenic or heated probe stations covering approximately 77 K to 500 K, ensuring full energy-window coverage from near the majority carrier band edge to mid-gap.

Applications

Interface state density analysis supports every phase of novel device development and manufacturing:

• Gate dielectric process optimization, including comparisons of thermal oxidation, ALD deposition, plasma nitridation, and post-oxidation NO/N2O or forming gas anneals
• SiC and GaN power device development, where Dit directly limits inversion channel mobility and threshold stability
• Advanced CMOS high-k metal gate integration and passivation interface qualification for FinFET and gate-all-around nodes
• Memory technologies, including charge-trap flash and ferroelectric FET stacks where interface and border traps control retention
• RF and mixed-signal device qualification through 1/f noise and linearity correlation with trap density
• Reliability qualification and lifetime modeling, correlating BTI and TDDB behavior with as-fabricated and stress-generated trap densities
• Failure analysis and lot acceptance testing on production wafers in accredited third-party laboratories
• Academic and industrial research on emerging materials, including Ga2O3, AlN, diamond, and 2D semiconductor heterostructures

FAQ

What is the minimum detectable Dit for each method?

Charge pumping offers the highest sensitivity, reaching approximately 109 cm-2eV-1. The conductance method and hi-lo C-V method typically reach 1010 to 1011 cm-2eV-1, while DLTS-based approaches cover the 1011 to 1013 cm-2eV-1 range depending on doping and capacitance signal levels.

Which method is recommended for SiC MOS devices?

Because SiC/SiO2 interfaces contain both fast interface states and near-interface oxide traps, a combined approach is recommended: hi-lo or conductance measurement for fast states, slow trap pumping or hysteresis analysis for slow traps, and temperature-dependent measurements to confirm trap exchange mechanisms.

What are the sample preparation requirements?

MOS/MIS capacitors should have a known gate area (diameter of at least 100 µm preferred), a low-resistance backside ohmic contact, and a dielectric free of pinholes. Transistors require accessible gate, source, drain, and body or substrate terminals.

Can measurements be performed on full wafers?

Yes. On-wafer probing with semi-automatic probe stations supports wafer sizes up to 300 mm, enabling wafer-level mapping of Dit uniformity for process control purposes.

What temperature range is available?

Standard measurements are performed at room temperature. Temperature-dependent characterization is available from approximately 77 K to 500 K to extend the accessible energy window within the bandgap and to extract trap activation energies.

How should results be interpreted for device design?

Reported results include Dit(E) spectra, extracted mid-gap and band-edge densities, time constants, and charge trapping indicators. Engineers typically target mid-gap Dit below approximately 1x1011 cm-2eV-1 for SiC power MOSFETs and below 1010 cm-2eV-1 for advanced silicon CMOS interfaces, with exact targets set by the specific device architecture and application requirements.